1. Field of the Invention
The invention relates to a state machine, and in particular to a state machine with a dynamic clock gating function, leading to a low power consumption.
2. Description of the Related Art
As shown in FIG. 1a, a traditional state machine includes a next state logic 10 and a current state logic 12. The current state logic 12 consists of a plurality of flip-flops. A clock signal is directly inputted to the clock input terminal of each flip-flop. Thus, the total power consumption caused by a state transition of the clock signal is estimated by the following formula: EQU .SIGMA.1/2C.sub.Li V.sup.2.function..sub.i
where the C.sub.Li is a total capacitance of all capacitors which are charged/discharged in the current state logic 12 following the state transition of the clock signal with a frequency of f.sub.i.
As an example, a traditional resettable D-type flip-flop is shown in FIG. 2.
In FIG. 2, an inverter 20 receives an external clock signal CK and then transmits a transfer control signal CKB. The transfer control signal CKB is reverted into a complementary transfer control signal CKB by an inverter 22, wherein the transfer control signal CKB and the complementary transfer control signal CKB are used to control the on/off states of a CMOS transmission gate.
When the external clock signal CK is at a low logic level, the transfer control signal CKB is at a high logic level and the complementary transfer control signal CKB is at a low logic level. At this point, transmission gates 24 and 26 are closed while transmission gates 28 and 30 are open. On the other hand, when the external clock CK is at a high logic level, the transfer control signal CKB is at a low logic level and the complementary transfer control signal CKB is at a high logic level. At this time, the transmission gates 24 and 26 are open while the transmission gates 28 and 30 are closed. In line with the state transition of the clock signal between the high and low logic levels, capacitors, including the input and output capacitor of the inverters 20 and 22 and the input capacitors of the transmission gates 24, 26, 28 and 30, are charged/discharged, causing a power consumption. No matter at which state the state machine is, the power consumption remains constant even if the state machine is at an idle state. This causes a problem of an excess power consumption.